This invention relates to a multiprocessor system in general and, more particularly to an interlock scheme in which intelligent buffer repeaters are used to connect busses together.
The use of a single bus in a multiprocessor system presents several difficulties. In order to accommodate several nodes on a bus, the electrical loading of the bus is significantly increased. This slows down the cycle time of the system.
One solution to the above problems is the use of two separate busses interconnected through a repeater. This serves to virtually extend the bus to accommodate several nodes while not actually increasing the electrical loading on the bus.
However, a difficulty arises with interlock transactions which must be passed through the repeater. When a device on the first bus generates an interlock read command to access memory, it must be sent through the repeater. If accepted by the memory, the interlock read command will lock the memory until an unlock write signal is generated. If the memory is already locked, then the interlock read command is stored in a buffer until an unlock write signal from the device unlocks the memory. Deadlock situations present themselves where the memory is locked, an interlock read is waiting in the buffer and an unlock write signal is behind the interlock read in the same buffer.